With multi-core processors are more widely applied to various technical fields, the advantages of strong parallel computing capability, low power consumption and high integration have been gradually accepted by the market. The salient feature of the multi-core processor is that the same task can be broken down to threads or processes of a plurality of cores for parallel running, and such parallelism brings a significant improvement of performance. However, while bringing the improvement of performance, the multi-core processor also brings a series of problems such as frequent communication tasks between cores and complex management on communication between cores, furthermore, with more and more cores being integrated on the same chip, this problem becomes more and more prominent. Therefore, a high speed and efficient communication device and method between cores become one of the key technologies for the chip of the multi-core processor.
In the related art, the communication between cores is generally based on a shared memory. Such as, the patent “Method and Device for Communicating between cores of the Multi-core Processor in Embedded Real-time Operating System” as described in Patent number CN200510087321, where a shared memory is used to realize a sharing message pool and a message data pipeline which are required by communication between cores. It is required operating system software to create a message queue in this method, and an operation of establishing pipelines for communication between cores is needed, and therefore the complexity is relatively high; more critically, in order to complete the consistency to access the multi-core shared message memory, it is required to use spin lock resources and additional synchronous operations such as applying for a lock and releasing a lock, these complex software interaction steps will greatly reduce the efficiency of communication between cores, at the same time, the reliability is reduced while greatly increasing the number of cores, and the separated message operation and interrupt notification mechanism also will lead to the reduction of the efficiency. In addition, the method based on the shared memory brings a larger increase of uncertainty on communication timeliness because the messages between cores must share the same bandwidth with data.
In order to solve the problems of high complexity and high time delay of the communication between cores mechanism based on the shared memory, some improved methods are also produced. Such as the patent “Method and System for Generating and Delivering Inter-Processor Interrupts in a Multi-Core Processor and in Certain Shared Memory Multi-Processor Systems” as described in patent number US20080988459, where a shared storage area is designated by operating a group of specialized Interrupt Mask Register (IMR) through software, and an interrupt between cores is automatically triggered to generate when a write operation aims at the designated shared storage area. However, the message is stored in a circular buffer of the shared memory area, and is still need to be performed by circular buffering access through a data structure realized by the software, and the interrupt generated by the message notification is generated by the IMR. It still needs to pre-set the IMR, and factors such as the separation of the register operation and the message operation and many software interaction steps directly lead to relatively large time delay and complex software programming of the communication between cores, so that the requirement of high-performance multi-core communication cannot be met. Meanwhile, the patent also fails to solve the problems of resource consumption and increased complexity brought by the fact that the mutual exclusion operation must be introduced in order to ensure the reliability of communication between cores.
Except for the major defects mentioned above that the existing technology of the communication between cores with low communication efficiency and the timeliness cannot being ensured, the existing communication between cores technology needs more hardware resources and more complex software processing steps when the number of cores is obviously increased, in a heterogeneous multi-core system, the differences in supporting the frequency of the core, the interface structure and the data structure also greatly increase the software complexity of the existing method of communication between cores, and the compatibility and reliability of the heterogeneous core communication program is insufficient. That is, the expandability and flexibility of the existing technology of the communication between cores is insufficient while adapting to the heterogeneous core and the increase in the number of cores.
Therefore, the problems of high complexity, poor timeliness and poor expandability during multi-core application exist in the related art.